For nondeterministic transaction requests over a double data rate (DDR) memory channel such as a DDR4 or DDR5 bus, the host and the device controller on the memory side have to assign proper transaction identifications (TIDs) for a host to identify which requests respond to the host with completed data or completion status at a time later than the previously issued transaction requests. To synchronize the device TID assignment or TID generator with the host side TID generator without additional bus resource or to embed or hide TID synchronizations within existing bus traffics, becomes a challenge. For writing data, to embed TID information of the write transaction into current cyclic redundancy check (CRC) bytes of a DDR4 (fourth-generation double data rate memory device) can make total channel overhead as high as 40.625% from 12.5%. For reading data, it would be too late for the host to find errors in a received TID. The TID should be synced to the received read request. Current proposals for a non-volatile dual in-line memory module for persistent memory (NVDIMM-P) also include reporting TID error by read data's error-correcting code (ECC) as interrupt to the host and using three handshaking pins as shared feedback error message bus. Enhancements are needed to address operations of a host and memory module to efficiently handle identification of transactions between the host and memory module.